![]() ![]() A simple example of this is a parity bit. The point I was trying to make is that an error correction code that is designed for correcting single bit errors from weak DRAM cells is not suitable for providing a very low rate of undetected DRAM errors, where very low rate means one undetected error per 100s of years (essentially no undetected DRAM errors).Īn error correction code that can reliably detect x errors is not still very likely to detect >x errors. The exact percentages of different fault modes probably has changed. I don’t know if DRAM vendors have done something to fix this problem since the NeRSC results. I am very surprised that NeRSC found DRAM row failures and DRAM bank failures to be so common for all three vendors. I agree with you that a memory test at power on would find permanent failures, but not the instant they happen. The only way NeRSC would be able to classify an error as a DRAM bank failure is by reading multiple rows in the DRAM bank and always getting an error, so that is not a temporary failure. A DRAM bank failure seems like a permanent failure. DRAM sense amplifiers compare the bit lines to a dummy cell so the problem could be a temporary problem with the value read from the dummy cell, such as from power supply noise. A DRAM row failure seems like something went wrong on the word line for a row or something when wrong on all the sense amplifiers for a row. I am not a DRAM circuit designer so I can only guess at the answers. I was wondering about the exact same questions you have.
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